This invention relates to the use of a sealing dielectric layer applied between a porous dielectric layer and a metal diffusion barrier layer. The sealing dielectric layer closes the pores on the surface and sidewalls of the porous dielectric layer. This invention allows the use of a thin metal diffusion barrier layer without creating pinholes in the metal diffusion barrier layer or without diffusion inside bulk of the porous material.
Traditionally, Physical Vapor Deposition (PVD) metal barrier materials like TaN are used to prevent interconnect metals, in particular copper (Cu) from diffusing into the dielectric layer on semiconductor devices. The trend to scale down design rules has led to the requirement to start using dielectric layers with a dielectric constant (Dk) lower than 4-4.2 (what is typically achieved for PECVD oxide dielectric films). As the industry starts to use dielectric layers having lower Dk values a certain amount of porosity will be required to achieve the lower Dk value especially if films below a Dk of 2.6. (xe2x80x9cporous dielectric filmsxe2x80x9d) The Dk will depend on the amount of porosity and also on the resin nature.
There are two groups of low dielectric materials, the spin-on dielectrics and CVD dielectric materials. The spin-on dielectrics can be divided in two groups, the organic and the inorganic spin-on dielectric materials. The CVD dielectric materials currently use an organosilane/organooxysilane precursor as active agent in combination with an oxidation agent to generate a low-k dielectric film. Regardless of how the low Dk films are produced, the low Dk films have a certain amount of porosity or intramolecular spacing.
The porosity in the low Dk films can cause problems with the metal diffusion barrier (e.g. the TaN layer) because there are pores inside and/or on top of the material. There is no difference between closed or open pore materials because closed pores will be etched open during the patterning of damascene structures. Both open and closed pore type of materials are sensitive to increased xe2x80x9cpinholexe2x80x9d formation in the metal diffusion barrier sputtered layer on top of these patterns. The pinhole formation may lead to reliability problems and potential paths for diffusion and degradation of the metal interconnects and the dielectric. Because of this, a thick layer of metal diffusion barrier is required to seal the pores and to avoid xe2x80x9cpinholesxe2x80x9d. Another problem is that in the case of metal barrier formation by Atomic Layer Chemical Vapor Deposition (AL CVD), in an open pore the metal barrier will be deposited inside the bulk of the low dielectric. Amorphous dielectric materials do not result in pinholes or deposition of the metal diffusion barrier layer in the bulk porous material.
This invention relates to the use of a sealing dielectric layer applied between the porous dielectric layer and the metal diffusion barrier layer. The sealing dielectric layer closes the pores on the surface and/or on the sidewall of the porous dielectric layer. This invention allows the use of thin metal diffusion barrier (e.g. TaN) layer without creating xe2x80x9cpinholesxe2x80x9d in the metal diffusion barrier layer.
The present invention relates to an improved integrated circuit having greater reliability. The circuit comprises a subassembly of solid-state devices formed typically on or in a silicon substrate. Metal wiring formed from conductive metals connects the devices within the subassembly. A sealing dielectric layer having a composition of SixCy:Hz, where x has a value of 10-50, preferably 25-35 atomic percent, y has a value of 1-66, preferably 30-40 atomic % and z has a value of 0.1-66, preferably 25-35 atomic %; and x+y+zxe2x89xa790 atomic % is formed on the patterned porous dielectric films. The use of a sealing dielectric layer avoids pinhole formation in the metal diffusion barrier.